; -> Hdr.UART
; definitions for uart used in stand-alone MIDI podule

OldOpt SETA {OPT}
 OPT OptNoList+OptNoP1List

MIDI_only_UARTOffset  * &2000   ; UART offset from podule base address in stand_alone MIDI podule
MIDI_UP_UARTOffset    * &3000   ; UART offset from podule base address in user-port + MIDI podule

MROffset    *     0   ; MR1/MR2 offset from UART base address
SROffset    *   &04   ; SR/CSR offset
CROffset    *   &08   ; ()/CR
HROffset    *   &0C   ; RHR/THR
ACROffset   *   &10   ; ()/ACR
IROffset    *   &14   ; ISR/IMR
CTUOffset   *   &18   ; CTU/CTUR
CTLOffset   *   &1C   ; CTL/CTLR

MR1       * 2_00010011 ; UART reg. 1. rxrdy irq, char error, no parity, 8b/c
MR2       * 2_00000111 ; UART reg. 2. normal, 1 stop bit
CSR       * 2_11011101 ; clock sel. reg. timer as baud source for tx and rx
CRResetMR * 2_00010000 ; reset the mr pointer to mr1
CRResetRx * 2_00100000 ; reset the receiver
CRResetTx * 2_00110000 ; reset the transmitter
CRResetEr * 2_01000000 ; reset the error status
CRResetBk * 2_01010000 ; reset the break change detect bit
CRStartCT * 2_10000000 ; start the counter/timer
CRenable  * 2_00000101 ; enable transmitter and receiver
CRdisable * 2_00001010 ; disable transmitter and receiver
SRRxBreak * 2_10000000 ; received break
SRRxFE    * 2_01000000 ; received framing error
SRRxOE    * 2_00010000 ; received overrun error
SRTxEMT   * 2_00001000 ; transmitter empty
SRTxRDY   * 2_00000100 ; transmitter ready
SRFFull   * 2_00000010 ; receiver FIFO full
SRRxRDY   * 2_00000001 ; receiver ready
ACR       * 2_01101000 ; auxiliary control reg. power up mode
RxRDYirq  * 2_00000100 ; normally interrupt on RxRDY only
TxRDYirq  * 2_00000001 ; OR with IMR when transmitting
CTUR      * 0
CTLR      * 2          ; counter timer set to 2   for div by 4

 OPT OldOpt

 END
